Collaborative Research: SHF: Medium: A hardware accelerator for satisfiability (SAT): Over — NSF Award to University of California
Boolean satisfiability (SAT) is a core problem in computing with broad, high-impact applications. A wide range of critical problems in industry and defense, e.g., in hardware and software design and verification, artificial intelligence, robotics, and drug discovery, use SAT solvers and often take weeks to complete on
| Award title | Collaborative Research: SHF: Medium: A hardware accelerator for satisfiability (SAT): Over |
|---|---|
| Award ID | 2505130 |
| Awardee | University of California-Berkeley |
| City | BERKELEY |
| State | CA |
| Amount obligated | $300,000 |
| Principal investigator | Pierluigi Nuzzo |
| Program | Software & Hardware Foundation |
| Start date | 10/01/2025 |
| Abstract | Boolean satisfiability (SAT) is a core problem in computing with broad, high-impact applications. A wide range of critical problems in industry and defense, e.g., in hardware and software design and verification, artificial intelligence, robotics, and drug discovery, use SAT solvers and often take weeks to complete on modern large-scale computing systems. This project will develop new types of accelerator chips custom-designed for SAT to reduce the time and energy required to solve all such impo |
| Source | NSF Awards |
$799/mo
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