SaTC: TTP: Medium: Hardware Intellectual Property Protection through Hybrid ASIC/TRAP Inte — NSF Award to University of California
As the semiconductor industry transitioned from an in-house fabrication model to a third-party foundry model, it provided widespread access to cutting edge technology at affordable cost and accelerated development of advanced electronic circuits. At the same time, it introduced new concerns regarding protection of the
| Award title | SaTC: TTP: Medium: Hardware Intellectual Property Protection through Hybrid ASIC/TRAP Inte |
|---|---|
| Award ID | 2604733 |
| Awardee | University of California-San Diego |
| City | LA JOLLA |
| State | CA |
| Amount obligated | $496,820 |
| Principal investigator | Yiorgos Makris |
| Program | Secure &Trustworthy Cyberspace |
| Start date | 12/15/2025 |
| Abstract | As the semiconductor industry transitioned from an in-house fabrication model to a third-party foundry model, it provided widespread access to cutting edge technology at affordable cost and accelerated development of advanced electronic circuits. At the same time, it introduced new concerns regarding protection of the intellectual property of these electronic circuits, whose blueprints must now be shared with globally distributed and potentially untrusted entities involved in the contemporary el |
| Source | NSF Awards |
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